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NXP Semiconductors /LPC5410x /SPI0 /INTENSET

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Interpret as INTENSET

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)RXRDYEN 0 (DISABLED)TXRDYEN 0 (DISABLED)RXOVEN 0 (DISABLED)TXUREN 0 (DISABLED)SSAEN 0 (DISABLED)SSDEN 0RESERVED 0 (DISABLED)MSTIDLEEN 0RESERVED

MSTIDLEEN=DISABLED, SSAEN=DISABLED, RXOVEN=DISABLED, TXUREN=DISABLED, RXRDYEN=DISABLED, SSDEN=DISABLED, TXRDYEN=DISABLED

Description

SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.

Fields

RXRDYEN

RX ready interrupt enable. Determines whether an interrupt occurs when receiver data is available.

0 (DISABLED): Disabled. No interrupt will be generated when receiver data is available.

1 (ENABLED): Enabled. An interrupt will be generated when receiver data is available in the RXDAT register.
TXRDYEN

TX ready interrupt enable. Determines whether an interrupt occurs when the transmitter holding register is available.

0 (DISABLED): Disabled. No interrupt will be generated when the transmitter holding register is available.

1 (ENABLED): Enabled. An interrupt will be generated when data may be written to TXDAT.
RXOVEN

RX overrun interrupt enable. Determines whether an interrupt occurs when a receiver overrun occurs. This happens in slave mode when there is a need for the receiver to move newly received data to the RXDAT register when it is already in use. The interface prevents receiver overrun in Master mode by not allowing a new transmission to begin when a receiver overrun would otherwise occur.

0 (DISABLED): Disabled. No interrupt will be generated when a receiver overrun occurs.

1 (ENABLED): Enabled. An interrupt will be generated if a receiver overrun occurs.
TXUREN

TX underrun interrupt enable. Determines whether an interrupt occurs when a transmitter underrun occurs. This happens in slave mode when there is a need to transmit data when none is available.

0 (DISABLED): Disabled. No interrupt will be generated when the transmitter underruns.

1 (ENABLED): Enabled. An interrupt will be generated if the transmitter underruns.
SSAEN

Slave select assert interrupt enable. Determines whether an interrupt occurs when the Slave Select is asserted.

0 (DISABLED): Disabled. No interrupt will be generated when any Slave Select transitions from deasserted to asserted.

1 (ENABLED): Enabled. An interrupt will be generated when any Slave Select transitions from deasserted to asserted.
SSDEN

Slave select deassert interrupt enable. Determines whether an interrupt occurs when the Slave Select is deasserted.

0 (DISABLED): Disabled. No interrupt will be generated when all asserted Slave Selects transition to deasserted.

1 (ENABLED): Enabled. An interrupt will be generated when all asserted Slave Selects transition to deasserted.
RESERVED

Reserved. Read value is undefined, only zero should be written.
MSTIDLEEN

Master idle interrupt enable

0 (DISABLED): Disabled. No interrupt will be generated when the SPI master function is idle.

1 (ENABLED): Enabled. An interrupt will be generated when the SPI master function is idle.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data